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1/57 february 2005 nand128-a, nand256-a nand512-a, nand01g-a 128 mbit, 256 mbit, 512 mbit, 1 gbit (x8/x16) 528 byte/264 word page, 1.8v/3v, nand flash memories features summary high density nand flash memories ? up to 1 gbit memory array ? up to 32 mbit spare area ? cost effective solutions for mass storage applications nand interface ? x8 or x16 bus width ? multiplexed address/ data ? pinout compatibility for all densities supply voltage ? 1.8v device: v dd = 1.7 to 1.95v ? 3.0v device: v dd = 2.7 to 3.6v page size ? x8 device: (512 + 16 spare) bytes ? x16 device: (256 + 8 spare) words block size ? x8 device: (16k + 512 spare) bytes ? x16 device: (8k + 256 spare) words page read / program ? random access: 12s (max) ? sequential access: 50ns (min) ? page program time: 200s (typ) copy back program mode ? fast page copy without external buffering fast block erase ? block erase time: 2ms (typ) status register electronic signature chip enable ?don?t care? option ? simple interface with microcontroller serial number option hardware data protection ? program/erase locked during power transitions figure 1. packages data integrity ? 100,000 program/erase cycles ? 10 years data retention rohs compliance ? lead-free components are compliant with the rohs directive development tools ? error correction code software and hardware models ? bad blocks management and wear leveling algorithms ? file system os native reference software ? hardware simulation models tsop48 12 x 20mm vfbga55 8 x 10 x 1mm tfbga55 8 x 10 x 1.2mm vfbga63 9 x 11 x 1mm tfbga63 9 x 11 x 1.2mm fbga usop48 12 x 17 x 0.65mm
nand128-a, nand256-a, nand512-a, nand01g-a 2/57 table 1. product list reference part number nand128-a nand128r3a nand128w3a nand128r4a nand128w4a nand256-a nand256r3a nand256w3a nand256r4a nand256w4a nand512-a nand512r3a nand512w3a nand512r4a nand512w4a nand01g-a nand01gr3a nand01gw3a nand01gr4a nand01gw4a
3/57 nand128-a, nand256-a, nand512-a, nand01g-a table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 1. product list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. tsop48 and usop48 connections, x8 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. tsop48 and usop48 connections, x16 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. fbga55 connections, x8 devices (top view through package) . . . . . . . . . . . . . . . . . . . 11 figure 7. fbga55 connections, x16 devices (top view through package) . . . . . . . . . . . . . . . . . . 12 figure 8. fbga63 connections, x8 devices (top view through package) . . . . . . . . . . . . . . . . . . . 13 figure 9. fbga63 connections, x16 devices (top view through package) . . . . . . . . . . . . . . . . . . 14 memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. valid blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 10.memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 inputs/outputs (i/o0-i/o7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 inputs/outputs (i/o8-i/o15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 address latch enable (al) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 command latch enable (cl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 chip enable (e ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 read enable (r ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 write enable (w ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 write protect (wp ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ready/busy (rb ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 6. address insertion, x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8
nand128-a, nand256-a, nand512-a, nand01g-a 4/57 table 7. address insertion, x16 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8. address definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 device operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 pointer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11.pointer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 12.pointer operations for programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 read memory array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 page read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 sequential row read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 13.read (a,b,c) operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 14.read block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 15.sequential row read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 16.sequential row read block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 17.page program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 10. copy back program addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 18.copy back operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 19.block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 read status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 write protection bit (sr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 p/e/r controller bit (sr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 error bit (sr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 sr5, sr4, sr3, sr2 and sr1 are reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 11. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 12. electronic signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 block replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 13. block failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 20.bad block management flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 21.garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 error correction code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 22.error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
5/57 nand128-a, nand256-a, nand512-a, nand01g-a behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 ibis simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 program and erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 14. program, erase times and program erase enduranc e cycles . . . . . . . . . . . . . . . . . . . 33 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 15. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 16. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 17. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 18. dc characteristics, 1.8v devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 19. dc characteristics, 3v devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 table 20. ac characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 21. ac characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 23.command latch ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 24.address latch ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 25.data input latch ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 26.sequential data output after read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 27.read status register ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 28.read electronic signature ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 29.page read a/ read b operation ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 30.read c operation, one page ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 31.page program ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 32.block erase ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 33.reset ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 ready/busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 34.ready/busy ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 figure 35.ready/busy load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 36.resistor value versus waveform timings for ready/busy signal . . . . . . . . . . . . . . . . 46 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 37.tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package outline . . . . . . . . . 47 table 22. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package mechanical data . 47 figure 38.usop48 ? lead plastic ultra thin small outline,12 x 17mm, package outline . . . . . . . 48 table 23. usop48 ? lead plastic ultra thin small outline, 12 x 17mm, package mechanical data48 figure 39.vfbga55 8 x 10mm - 6x8 active ball array, 0.80mm pitch, package outline . . . . . . . . 49 table 24. vfbga55 8 x 10mm - 6x8 ball array, 0.80mm pitch, package mechanical data . . . . . . 49 figure 40.tfbga55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, package outline . . . . . . . . 50 table 25. tfbga55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, package mechanical data 50 figure 41.vfbga63 9x11mm - 6x8 active ball array, 0.80mm pitch, package outline . . . . . . . . . 51 table 26. vfbga63 9x11mm - 6x8 active ball array, 0.80mm pitch, package mechanical data . . 51 figure 42.tfbga63 9x11mm - 6x8 active ball array, 0.80mm pitch, package outline. . . . . . . . . . 52 table 27. tfbga63 9x11mm - 6x8 active ball array, 0.80mm pitch, package mechanical data . . 52
nand128-a, nand256-a, nand512-a, nand01g-a 6/57 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 28. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 appendix a.hardware interface examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 43.connection to microcontroller, without glue logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 44.connection to microcontroller, with glue logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 45.building storage modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 29. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
7/57 nand128-a, nand256-a, nand512-a, nand01g-a summary description the nand flash 528 byte/ 264 word page is a family of non-volatile flash memories that uses the single level cell (slc) nand cell technology. it is referred to as the small page family. the de- vices range from 128mbits to 1gbit and operate with either a 1.8v or 3v voltage supply. the size of a page is either 528 bytes (512 + 16 spare) or 264 words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width. the address lines are multiplexed with the data in- put/output signals on a multiplexed x8 or x16 in- put/output bus. this interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. each block can be programmed and erased over 100,000 cycles. to extend the lifetime of nand flash devices it is strongly recommended to imple- ment an error correction code (ecc). a write protect pin is available to give a hardware protec- tion against program and erase operations. the devices feature an open-drain ready/busy output that can be used to identify if the program/ erase/read (p/e/r) controller is currently active. the use of an open-drain output allows the ready/ busy pins from several memories to be connected to a single pull-up resistor. a copy back command is available to optimize the management of defective blocks. when a page program operation fails, the data can be pro- grammed in another page without having to re- send the data to be programmed. the devices are available in the following packag- es: tsop48 12 x 20mm for all products usop48 12 x 17 x 0.65mm for 128mb, 256mb and 512mb products vfbga55 (8 x 10 x 1mm, 6 x 8 ball array, 0.8mm pitch) for 128mb and 256mb products tfbga55 (8 x 10 x 1.2mm, 6 x 8 ball array, 0.8mm pitch) for 512mb dual die product vfbga63 (9 x 11 x 1mm, 6 x 8 ball array, 0.8mm pitch) for the 512mb product tfbga63 (9 x 11 x 1.2mm, 6 x 8 ball array, 0.8mm pitch) for the 1gb dual die product two options are available for the nand flash family: chip enable don?t care, which allows code to be directly downloaded by a microcontroller, as chip enable transitions during the latency time do not stop the read operation. a serial number, which allows each device to be uniquely identified. the serial number options is subject to an nda (non disclosure agreement) and so not described in the datasheet. for more details of this option contact your nearest st sales office. for information on how to order these options refer to table 28., ordering information scheme . de- vices are shipped from the factory with block 0 al- ways valid and the memory content bits, in valid blocks, erased to ?1?. see table 2., product description , for all the de- vices available in the family.
nand128-a, nand256-a, nand512-a, nand01g-a 8/57 table 2. product description note: 1. dual die device. figure 2. logic diagram table 3. signal names reference part number density bus width page size block size memory array operating vo ltag e timings package random access max sequential access min page program typical block erase typical nand128-a nand128r3a 128mbit x8 512+16 bytes 16k+512 bytes 32 pages x 1024 blocks 1.7 to 1.95v 12s 60ns 200s 2ms tsop48 usop48 vfbga55 nand128w3a 2.7 to 3.6v 12s 50ns 200s nand128r4a x16 256+8 words 8k+256 words 1.7 to 1.95v 12s 60ns 200s nand128w4a 2.7 to 3.6v 12s 50ns 200s nand256-a nand256r3a 256mbit x8 512+16 bytes 16k+512 bytes 32 pages x 2048 blocks 1.7 to 1.95v 12s 60ns 200s 2ms tsop48 usop48 vfbga55 nand256w3a 2.7 to 3.6v 12s 50ns 200s nand256r4a x16 256+8 words 8k+256 words 1.7to 1.95v 12s 60ns 200s nand256w4a 2.7 to 3.6v 12s 50ns 200s nand512-a (1) nand512r3a 512mbit x8 512+16 bytes 16k+512 bytes 32 pages x 4096 blocks 1.7to 1.95v 12s 60ns 200s 2ms tfbga55 nand512w3a 2.7 to 3.6v 12s 50ns 200s nand512r4a x16 256+8 words 8k+256 words 1.7 to 1.95v 12s 60ns 200s nand512w4a 2.7 to 3.6v 12s 50ns 200s nand512-a nand512r3a 512mbit x8 512+16 bytes 16k+512 bytes 32 pages x 4096 blocks 1.7to 1.95v 15s 60ns 200s 2ms tsop48 usop48 vfbga63 nand512w3a 2.7 to 3.6v 12s 50ns 200s nand512r4a x16 256+8 words 8k+256 words 1.7 to 1.95v 15s 60ns 200s nand512w4a 2.7 to 3.6v 12s 50ns 200s nand01g-a nand01gr3a 1gbit x8 512+16 bytes 16k+512 bytes 32 pages x 8192 blocks 1.7 to 1.95v 15s 60ns 200s 2ms tsop48 tfbga63 nand01gw3a 2.7 to 3.6v 12s 50ns 200s nand01gr4a x16 256+8 words 8k+256 words 1.7 to 1.95v 15s 60ns 200s nand01gw4a 2.7 to 3.6v 12s 50ns 200s ai07557c w i/o8-i/o15, x16 v dd nand flash e v ss wp al cl rb r i/o0-i/o7, x8/x16 i/o8-15 data input/outputs for x16 devices i/o0-7 data input/outputs, address inputs, or command inputs for x8 and x16 devices al address latch enable cl command latch enable e chip enable r read enable rb ready/busy (open-drain output) w write enable wp write protect v dd supply voltage v ss ground nc not connected internally du do not use
9/57 nand128-a, nand256-a, nand512-a, nand01g-a figure 3. logic block diagram address register/counter command interface logic p/e/r controller, high voltage generator wp i/o buffers & latches i/o8-i/o15, x16 e w ai07561c r y decoder page buffer nand flash memory array x decoder i/o0-i/o7, x8/x16 command register cl al rb
nand128-a, nand256-a, nand512-a, nand01g-a 10/57 figure 4. tsop48 and usop48 connections, x8 devices figure 5. tsop48 and usop48 connections, x16 devices i/o3 i/o2 i/o6 r rb nc i/o4 i/o7 ai07585b nand flash (x8) 12 1 13 24 25 36 37 48 e i/o1 nc nc nc nc nc nc nc wp w nc nc nc v ss v dd al nc nc cl nc i/o5 nc nc nc i/o0 nc nc nc nc nc v dd nc nc nc v ss nc nc nc nc i/o3 i/o9 i/o2 i/o6 r rb nc i/o14 i/o12 i/o10 i/o4 i/o7 ai07559b nand flash (x16) 12 1 13 24 25 36 37 48 i/o8 e i/o1 i/o11 nc nc nc nc nc nc nc wp w nc nc nc v ss v dd al nc nc cl nc i/o13 i/o15 i/o5 v ss nc v ss i/o0 nc nc nc nc nc v dd
11/57 nand128-a, nand256-a, nand512-a, nand01g-a figure 6. fbga55 connections, x8 devices (top view through package) ai09366b i/o7 wp i/o4 i/o3 nc v dd i/o5 v dd nc h v ss i/o6 d e cl c nc nc b du nc w nc a 8 7 6 5 4 3 2 1 nc nc nc nc g f e i/o0 al nc nc nc nc nc nc nc nc nc nc v ss nc nc nc nc rb i/o2 nc du i/o1 r nc nc nc v ss du du du du du m l k j
nand128-a, nand256-a, nand512-a, nand01g-a 12/57 figure 7. fbga55 connections, x16 devices (top view through package) ai09365b i/o15 wp i/o4 i/o11 i/o10 v dd i/o6 v dd i/o3 h v ss i/o13 d e cl c nc nc b du nc w nc a 8 7 6 5 4 3 2 1 nc nc nc nc g f e i/o1 al nc nc nc nc nc nc i/o7 i/o5 i/o14 i/o12 v ss nc nc nc nc rb i/o2 i/o0 du i/o9 r nc nc i/o8 v ss du du du du du m l k j
13/57 nand128-a, nand256-a, nand512-a, nand01g-a figure 8. fbga63 connections, x8 devices (top view through package) ai07586b i/o7 wp i/o4 i/o3 nc v dd i/o5 v dd nc h v ss i/o6 d e cl c nc nc b du nc w nc a 8 7 6 5 4 3 2 1 nc nc nc nc g f e i/o0 al du nc nc nc nc nc nc nc nc nc nc v ss nc nc nc nc rb i/o2 du nc du i/o1 10 9 r nc nc nc v ss du du du du du du du du du du du m l k j
nand128-a, nand256-a, nand512-a, nand01g-a 14/57 figure 9. fbga63 connections, x16 devices (top view through package) ai07560b i/o15 wp i/o4 i/o11 i/o10 v dd i/o6 v dd i/o3 h v ss i/o13 d e cl c nc nc b du nc w nc a 8 7 6 5 4 3 2 1 nc nc nc nc g f e i/o1 al du nc nc nc nc nc nc i/o7 i/o5 i/o14 i/o12 v ss nc nc nc nc rb i/o2 du i/o0 du i/o9 10 9 r nc nc i/o8 v ss du du du du du du du du du du du m l k j
15/57 nand128-a, nand256-a, nand512-a, nand01g-a memory array organization the memory array is made up of nand structures where 16 cells are connected in series. the memory array is organized in blocks where each block contains 32 pages. the array is split into two areas, the main area and the spare area. the main area of the array is used to store data whereas the spare area is typically used to store error correction codes, software flags or bad block identification. in x8 devices the pages are split into a main area with two half pages of 256 bytes each and a spare area of 16 bytes. in the x16 devices the pages are split into a 256 word main area and an 8 word spare area. refer to figure 10., memory array or- ganization . bad blocks the nand flash 528 byte/ 264 word page devic- es may contain bad blocks, that is blocks that con- tain one or more invalid bits whose reliability is not guaranteed. additional bad blocks may develop during the lifetime of the device. the bad block information is written prior to ship- ping (refer to bad block management section for more details). table 4. shows the minimum number of valid blocks in each device. the values shown include both the bad blocks that are present when the de- vice is shipped and the bad blocks that could de- velop later on. these blocks need to be managed using bad blocks management, block replacement or error correction codes (refer to software algo- rithms section). table 4. valid blocks figure 10. memory array organization density of device min max 1gbit 8032 8192 512mbits 4016 4096 256mbits 2008 2048 128mbits 1004 1024 ai07587 block = 32 pages page = 528 bytes (512+16) 512 bytes 512 bytes spare area 2nd half page (256 bytes) 16 bytes block 8 bits 16 bytes 8 bits page page buffer, 512 bytes 1st half page (256 bytes) block = 32 pages page = 264 words (256+8) 256 words 256 words spare area main area 8 words 16 bits 8 words 16 bits page buffer, 264 words block page x8 devices x16 devices
nand128-a, nand256-a, nand512-a, nand01g-a 16/57 signal descriptions see figure 2., logic diagram , and table 3., signal names , for a brief overview of the sig- nals connected to this device. inputs/outputs (i/o0-i/o7). input/outputs 0 to 7 are used to input the selected address, output the data during a read operation or input a command or data during a write operation. the inputs are latched on the rising edge of write enable. i/o0-i/ o7 are left floating when the device is deselected or the outputs are disabled. inputs/outputs (i/o8-i/o15). input/outputs 8 to 15 are only available in x16 devices. they are used to output the data during a read operation or input data during a write operation. command and address inputs only require i/o0 to i/o7. the inputs are latched on the rising edge of write enable. i/o8-i/o15 are left floating when the de- vice is deselected or the outputs are disabled. address latch enable (al). the address latch enable activates the latching of the address inputs in the command interface. when al is high, the inputs are latched on the rising edge of write en- able. command latch enable (cl). the command latch enable activates the latching of the com- mand inputs in the command interface. when cl is high, the inputs are latched on the rising edge of write enable. chip enable (e ). the chip enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. when chip enable is low, v il , the device is selected. while the device is busy programming or erasing, chip enable transitions to high, v ih , are ignored and the device does not revert to the standby mode. while the device is busy reading: the chip enable input should be held low during the whole busy time (t blbh1 ) for devices that do not present the chip enable don?t care option. otherwise, the read operation in progress is interrupted and the device reverts to the standby mode. for devices that feature the chip enable don't care option, chip enable going high during the busy time (t blbh1 ) will not interrupt the read operation and the device will not revert to the standby mode. read enable (r ). the read enable, r , controls the sequential data output during read opera- tions. data is valid t rlqv after the falling edge of r . the falling edge of r also increments the internal column address counter by one. write enable (w ). the write enable input, w , controls writing to the command interface, input address and data latches. both addresses and data are latched on the rising edge of write en- able. during power-up and power-down a recovery time of 1s (min) is required before the command inter- face is ready to accept a command. it is recom- mended to keep write enable high during the recovery time. write protect (wp ). the write protect pin is an input that gives a hardware protection against un- wanted program or erase operations. when write protect is low, v il , the device does not accept any program or erase operations. it is recommended to keep the write protect pin low, v il , during power-up and power-down. ready/busy (rb ). the ready/busy output, rb , is an open-drain output that can be used to identify if the p/e/r controller is currently active. when ready/busy is low, v ol , a read, program or erase operation is in progress. when the operation completes ready/busy goes high, v oh . the use of an open-drain output allows the ready/ busy pins from several memories to be connected to a single pull-up resistor. a low will then indicate that one, or more, of the memories is busy. refer to the ready/busy signal electrical charac- teristics section for details on how to calculate the value of the pull-up resistor. v dd supply voltage. v dd provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). an internal voltage detector disables all functions whenever v dd is below 2.5v (for 3v devices) or 1.5v (for 1.8v devices) to protect the device from any involuntary program/erase during power-tran- sitions. each device in a system should have v dd decou- pled with a 0.1f capacitor. the pcb track widths should be sufficient to carry the required program and erase currents v ss ground. ground, v ss, is the reference for the power supply. it must be connected to the sys- tem ground.
17/57 nand128-a, nand256-a, nand512-a, nand01g-a bus operations there are six standard bus operations that control the memory. each of these is described in this section, see table 5., bus operations , for a sum- mary. command input command input bus operations are used to give commands to the memory. command are accept- ed when chip enable is low, command latch en- able is high, address latch enable is low and read enable is high. they are latched on the ris- ing edge of the write enable signal. only i/o0 to i/o7 are used to input commands. see figure 23. and table 20. for details of the tim- ings requirements. address input address input bus operations are used to input the memory address. three bus cycles are required to input the addresses for the 128mb and 256mb de- vices and four bus cycles are required to input the addresses for the 512mb and 1gb devices (refer to tables 6 and 7 , address insertion). the addresses are accepted when chip enable is low, address latch enable is high, command latch enable is low and read enable is high. they are latched on the rising edge of the write enable signal. only i/o0 to i/o7 are used to input addresses. see figure 24. and table 20. for details of the tim- ings requirements. data input data input bus operations are used to input the data to be programmed. data is accepted only when chip enable is low, address latch enable is low, command latch enable is low and read enable is high. the data is latched on the rising edge of the write enable signal. the data is input sequentially using the write enable signal. see figure 25. and table 20. and table 21. for de- tails of the timings requirements. data output data output bus operations are used to read: the data in the memory array, the status register, the electronic signature and the serial number. data is output when chip enable is low, write en- able is high, address latch enable is low, and command latch enable is low. the data is output sequentially using the read en- able signal. see figure 26. and table 21. for details of the tim- ings requirements. write protect write protect bus operations are used to protect the memory against program or erase operations. when the write protect signal is low the device will not accept program or erase operations and so the contents of the memory array cannot be al- tered. the write protect signal is not latched by write enable to ensure protection even during power-up. standby when chip enable is high the memory enters standby mode, the device is deselected, outputs are disabled and power consumption is reduced. table 5. bus operations note: 1. only for x16 devices. 2. wp must be v ih when issuing a program or erase command. bus operation e al cl r w wp i/o0 - i/o7 i/o8 - i/o15 (1) command input v il v il v ih v ih rising x (2) command x address input v il v ih v il v ih rising x address x data input v il v il v il v ih rising x data input data input data output v il v il v il falling v ih x data output data output write protect x x x x x v il xx standby v ih xxxxx x x
nand128-a, nand256-a, nand512-a, nand01g-a 18/57 table 6. address insertion, x8 devices note: 1. a8 is set low or high by the 00h or 01h command, see pointer operations section. 2. any additional address input cycles will be ignored. 3. the 4th cycle is only required for 512mb and 1gb devices. table 7. address insertion, x16 devices note: 1. a8 is don?t care in x16 devices. 2. any additional address input cycles will be ignored. 3. the 01h command is not used in x16 devices. 4. the 4th cycle is only required for 512mb and 1gb devices. table 8. address definitions bus cycle i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 1 st a7 a6 a5 a4 a3 a2 a1 a0 2 nd a16 a15 a14 a13 a12 a11 a10 a9 3 rd a24 a23 a22 a21 a20 a19 a18 a17 4 th(4) v il v il v il v il v il v il a26 a25 bus cycle i/o8- i/o15 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 1 st x a7 a6 a5 a4 a3 a2 a1 a0 2 nd x a16 a15 a14 a13 a12 a11 a10 a9 3 rd x a24 a23 a22 a21 a20 a19 a18 a17 4 th(4) x v il v il v il v il v il v il a26 a25 address definition a0 - a7 column address a9 - a26 page address a9 - a13 address in block a14 - a26 block address a8 a8 is set low or high by the 00h or 01h command, and is don?t care in x16 devices
19/57 nand128-a, nand256-a, nand512-a, nand01g-a command set all bus write operations to the device are interpret- ed by the command interface. the commands are input on i/o0-i/o7 and are latched on the rising edge of write enable when the command latch enable signal is high. device operations are se- lected by writing specific commands to the com- mand register. the two-step command sequences for program and erase operations are imposed to maximize data security. the commands are summarized in table 9., commands . table 9. commands note: 1. the bus cycles are only shown for issu ing the codes. the cycles required to input the addresses or input/output data are not shown. 2. any undefined command sequence will be ignored by the device. command bus write operations (1) command accepted during busy 1 st cycle 2 nd cycle 3 rd cycle read a 00h - - read b 01h (2) - - read c 50h - - read electronic signature 90h - - read status register 70h - - ye s page program 80h 10h - copy back program 00h 8ah 10h block erase 60h d0h - reset ffh - - ye s
nand128-a, nand256-a, nand512-a, nand01g-a 20/57 device operations pointer operations as the nand flash memories contain two differ- ent areas for x16 devices and three different areas for x8 devices (see figure 11. ) the read command codes (00h, 01h, 50h) are used to act as pointers to the different areas of the memory array (they se- lect the most significant column address). the read a and read b commands act as point- ers to the main memory area. their use depends on the bus width of the device. in x16 devices the read a command (00h) sets the pointer to area a (the whole of the main area) that is words 0 to 255. in x8 devices the read a command (00h) sets the pointer to area a (the first half of the main area) that is bytes 0 to 255, and the read b command (01h) sets the pointer to area b (the second half of the main area) that is bytes 256 to 511. in both the x8 and x16 devices the read c com- mand (50h), acts as a pointer to area c (the spare memory area) that is bytes 512 to 527 or words 256 to 263. once the read a and read c commands have been issued the pointer remains in the respective areas until another pointer code is issued. howev- er, the read b command is effective for only one operation, once an operation has been executed in area b the pointer returns automatically to area a. the pointer operations can also be used before a program operation, that is the appropriate code (00h, 01h or 50h) can be issued before the pro- gram command 80h is issued (see figure 12. ). figure 11. pointer operations ai07592 area a (00h) a area b (01h) area c (50h) bytes 0- 255 bytes 256-511 bytes 512 -527 c b pointer (00h,01h,50h) page buffer area a (00h) a area c (50h) words 0- 255 words 256 -263 c pointer (00h,50h) page buffer x8 devices x16 devices
21/57 nand128-a, nand256-a, nand512-a, nand01g-a figure 12. pointer operations for programming ai07591 i/o address inputs data input 10h 80h areas a, b, c can be programmed depending on how much data is input. subsequent 00h commands can be omitted. area a 00h address inputs data input 10h 80h 00h i/o address inputs data input 10h 80h areas b, c can be programmed depending on how much data is input. the 01h command must be re-issued before each program. area b 01h address inputs data input 10h 80h 01h i/o address inputs data input 10h 80h only areas c can be programmed. subsequent 50h commands can be omitted. area c 50h address inputs data input 10h 80h 50h
nand128-a, nand256-a, nand512-a, nand01g-a 22/57 read memory array each operation to read the memory area starts with a pointer operation as shown in the pointer operations section. once the area (main or spare) has been selected using the read a, read b or read c commands four bus cycles (for 512mb and 1gb devices) or three bus cycles (for 128mb and 256mb devices) are required to input the ad- dress (refer to table 6. ) of the data to be read. the device defaults to read a mode after power- up or a reset operation. when reading the spare area addresses: a0 to a3 (x8 devices) a0 to a2 (x16 devices) are used to set the start address of the spare area while addresses: a4 to a7 (x8 devices) a3 to a7 (x16 devices) are ignored. once the read a or read c commands have been issued they do not need to be reissued for subsequent read operations as the pointer re- mains in the respective area. however, the read b command is effective for only one operation, once an operation has been executed in area b the pointer returns automatically to area a and so another read b command is required to start an- other read operation in area b. once a read command is issued three types of op- erations are available: random read, page read and sequential row read. random read. each time the command is is- sued the first read is random read. page read. after the random read access the page data is transferred to the page buffer in a time of t whbh (refer to table 21. for value). once the transfer is complete the ready/busy signal goes high. the data can then be read out sequen- tially (from selected column address to last column address) by pulsing the read enable signal. sequential row read. after the data in last col- umn of the page is output, if the read enable sig- nal is pulsed and chip enable remains low then the next page is automatically loaded into the page buffer and the read operation continues. a sequential row read operation can only be used to read within a block. if the block changes a new read command must be issued. refer to figure 15. and figure 16. for details of se- quential row read operations. to terminate a sequential row read operation set the chip enable signal to high for more than t ehel . sequential row read is not available when the chip enable don't care option is enabled.
23/57 nand128-a, nand256-a, nand512-a, nand01g-a figure 13. read (a,b,c) operations figure 14. read block diagrams note: 1. highest address depends on device density. cl e w al r i/o rb 00h/ 01h/ 50h ai07595 busy command code address input data output (sequentially) tblbh1 (read) ai07596 a0-a7 a9-a26 (1) area a (1st half page) read a command, x8 devices area b (2nd half page) area c (spare) area a (main area) area c (spare) a0-a7 read a command, x16 devices a0-a7 read b command, x8 devices area a (1st half page) area b (2nd half page) area c (spare) a0-a3 (x8) a0-a2 (x16) read c command, x8/x16 devices area a area a/ b area c (spare) a9-a26 (1) a9-a26 (1) a9-a26 (1) a4-a7 (x8), a3-a7 (x16) are don't care
nand128-a, nand256-a, nand512-a, nand01g-a 24/57 figure 15. sequential row read operations figure 16. sequential row read block diagrams i/o rb address inputs ai07597 1st page output busy tblbh1 (read busy time) 00h/ 01h/ 50h command code 2nd page output nth page output busy busy tblbh1 tblbh1 ai07598 block area a (1st half page) read a command, x8 devices area b (2nd half page) area c (spare) area a (main area) area c (spare) read a command, x16 devices read b command, x8 devices read c command, x8/x16 devices area a area a/ b a rea c (spare) area a (1st half page) area b (2nd half page) area c (spare) 1st page 2nd page nth page 1st page 2nd page nth page 1st page 2nd page nth page 1st page 2nd page nth page block block block
25/57 nand128-a, nand256-a, nand512-a, nand01g-a page program the page program operation is the standard oper- ation to program data to the memory array. the main area of the memory array is pro- grammed by page, however partial page program- ming is allowed where any number of bytes (1 to 528) or words (1 to 264) can be programmed. the maximum number of consecutive partial page program operations allowed in the same page is three. after exceeding this a block erase com- mand must be issued before any further program operations can take place in that page. before starting a page program operation a point- er operation can be performed to point to the area to be programmed. refer to the pointer opera- tions section and figure 12. for details. each page program operation consists of five steps (see figure 17. ): 1. one bus cycle is requir ed to setup the page program command 2. four bus cycles are then required to input the program address (refer to table 6. ) 3. the data is then input (up to 528 bytes/ 264 words) and loaded into the page buffer 4. one bus cycle is required to issue the confirm command to start the p/e/r controller. 5. the p/e/r controller then programs the data into the array. once the program operation has started the sta- tus register can be read using the read status register command. during program operations the status register will only flag errors for bits set to '1' that have not been successfully programmed to '0'. during the program operation, only the read sta- tus register and reset commands will be accept- ed, all other commands will be ignored. once the program operation has completed the p/ e/r controller bit sr6 is set to ?1? and the ready/ busy signal goes high. the device remains in read status register mode until another valid command is written to the com- mand interface. figure 17. page program operation note: before starting a page program operation a pointer operation can be performed. refer to pointer operations section for details. i/o rb address inputs sr0 ai07566 data input 10h 70h 80h page program setup code confirm code read status register busy tblbh2 (program busy time)
nand128-a, nand256-a, nand512-a, nand01g-a 26/57 copy back program the copy back program operation is used to copy the data stored in one page and reprogram it in an- other page. the copy back program operation does not re- quire external memory and so the operation is faster and more efficient because the reading and loading cycles are not r equired. the operation is particularly useful when a portion of a block is up- dated and the rest of the block needs to be copied to the newly assigned block. if the copy back program operation fails an error is signalled in the status register. however as the standard external ecc cannot be used with the copy back operation bit error due to charge loss cannot be detected. for this reason it is recom- mended to limit the number of copy back opera- tions on the same data and or to improve the performance of the ecc. the copy back program operation requires three steps: 1. the source page must be read using the read a command (one bus write cycle to setup the command and then 4 bus write cycles to input the source page address). this operation copies all 264 words/ 528 bytes from the page into the page buffer. 2. when the device returns to the ready state (ready/busy high), the second bus write cycle of the command is given with the 4 bus cycles to input the target page address. refer to table 10. for the addresses that must be the same for the source and target pages. 3. then the confirm command is issued to start the p/e/r controller. after a copy back program operation, a partial- page program is not allowed in the target page un- til the block has been erased. see figure 18. for an example of the copy back operation. table 10. copy back program addresses note: 1. dd = dual die. figure 18. copy back operation density same address for source and target pages 128 mbit a23 256 mbit a24 512 mbit a25 512 mbit dd (1) a24, a25 1 gbit dd (1) a25, a26 i/o rb source address inputs sr0 ai07590b 8ah 70h 00h copy back code read code read status register target address inputs tblbh1 (read busy time) 10h busy tblbh2 (program busy time)
27/57 nand128-a, nand256-a, nand512-a, nand01g-a block erase erase operations are done one block at a time. an erase operation sets all of the bits in the ad- dressed block to ?1?. all previous data in the block is lost. an erase operation consists of three steps (refer to figure 19. ): 1. one bus cycle is required to setup the block erase command. 2. only three bus cycles for 512mb and 1gb devices, or two for 128mb and 256mb devices are required to input the block address. the first cycle (a0 to a7) is not required as only addresses a14 to a26 (highest address depends on device density) are valid, a9 to a13 are ignored. in the last address cycle i/o2 to i/o7 must be set to v il . 3. one bus cycle is required to issue the confirm command to start the p/e/r controller. once the erase operation has completed the sta- tus register can be checked for errors. figure 19. block erase operation reset the reset command is used to reset the com- mand interface and status register. if the reset command is issued during any operation, the op- eration will be aborted. if it was a program or erase operation that was aborted, the contents of the memory locations being modified will no longer be valid as the data will be partially programmed or erased. if the device has already been reset then the new reset command will not be accepted. the ready/busy signal goes low for t blbh4 after the reset command is issued. the value of t blbh4 depends on the operation that the device was per- forming when the command was issued, refer to table 21. for the values. i/o rb block address inputs sr0 ai07593 d0h 70h 60h block erase setup code confirm code read status register busy tblbh3 (erase busy time)
nand128-a, nand256-a, nand512-a, nand01g-a 28/57 read status register the device contains a status register which pro- vides information on the current or previous pro- gram or erase operation. the various bits in the status register convey information and errors on the operation. the status register is read by issuing the read status register command. the status register in- formation is present on the output data bus (i/o0- i/o7) on the falling edge of chip enable or read enable, whichever occurs last. when several memories are connected in a system, the use of chip enable and read enable signals allows the system to poll each device separately, even when the ready/busy pins are common-wired. it is not necessary to toggle the chip enable or read en- able signals to update the contents of the status register. after the read status register command has been issued, the device remains in read status register mode until another command is issued. therefore if a read status register command is issued during a random read cycle a new read command must be issued to continue with a page read or sequential row read operation. the status register bits are summarized in table 11., status register bits . refer to table 11. in conjunction with the following text descriptions. write protection bit (sr7). the write protection bit can be used to identify if the device is protected or not. if the write protection bit is set to ?1? the de- vice is not protected and program or erase opera- tions are allowed. if the write protection bit is set to ?0? the device is protected and program or erase operations are not allowed. p/e/r controller bit (sr6). the program/erase/ read controller bit indicates whether the p/e/r controller is active or inactive. when the p/e/r controller bit is set to ?0?, the p/e/r controller is active (device is busy); when the bit is set to ?1?, the p/e/r controller is inactive (device is ready). error bit (sr0). the error bit is used to identify if any errors have been detected by the p/e/r con- troller. the error bit is set to ?1? when a program or erase operation has failed to write the correct data to the memory. if the error bit is set to ?0? the oper- ation has completed successfully. sr5, sr4, sr3, sr2 and sr1 are reserved.
29/57 nand128-a, nand256-a, nand512-a, nand01g-a table 11. status register bits read electronic signature the device contains a manufacturer code and de- vice code. to read these codes two steps are re- quired: 1. first use one bus write cycle to issue the read electronic signature command (90h) 2. then perform two bus read operations ? the first will read the manufacturer code and the second, the device code. further bus read operations will be ignored. refer to table 12., electronic signature , for infor- mation on the addresses. table 12. electronic signature bit name logic level definition sr7 write protection '1' not protected '0' protected sr6 program/ erase/ read controller '1' p/e/r c inactive, device ready '0' p/e/r c active, device busy sr5, sr4, sr3, sr2, sr1 reserved don?t care sr0 generic error ?1? error ? operation failed ?0? no error ? operation successful part number manufacturer code device code nand128r3a 20h 33h nand128w3a 73h nand128r4a 0020h 0043h nand128w4a 0053h nand256r3a 20h 35h nand256w3a 75h nand256r4a 0020h 0045h nand256w4a 0055h nand512r3a 20h 36h nand512w3a 76h nand512r4a 0020h 0046h nand512w4a 0056h nand01gr3a 20h 39h nand01gw3a 79h nand01gr4a 0020h 0049h nand01gw4a 0059h
nand128-a, nand256-a, nand512-a, nand01g-a 30/57 software algorithms this section gives information on the software al- gorithms that st recommends to implement to manage the bad blocks and extend the lifetime of the nand device. nand flash memories are programmed and erased by fowler-nordheim tunneling using a high voltage. exposing the device to a high voltage for extended periods can cause the oxide layer to be damaged. for this reason, the number of program and erase cycles is limited (see table 14. for val- ue) and it is recommended to implement garbage collection, a wear-leveling algorithm and an er- ror correction code, to extend the number of pro- gram and erase cycles and increase the data retention. to help integrate a nand memory into an applica- tion st microelectronics can provide: file system os native reference software, which supports the basic commands of file management. contact the nearest st microelectronics sales of- fice for more details. bad block management devices with bad blocks have the same quality level and the same ac and dc characteristics as devices where all the blocks are valid. a bad block does not affect the performance of valid blocks be- cause it is isolated from the bit line and common source line by a select transistor. the devices are supplied with all the locations in- side valid blocks erased (ffh). the bad block in- formation is written prior to shipping. any block where the 6th byte/ 1st word in the spare area of the 1st page does not contain ffh is a bad block. the bad block information must be read before any erase is attempted as the bad block informa- tion may be erased. for the system to be able to recognize the bad blocks based on the original in- formation it is recommended to create a bad block table following the flowchart shown in figure 20. block replacement over the lifetime of the device additional bad blocks may develop. in this case the block has to be replaced by copying the data to a valid block. these additional bad blocks can be identified as attempts to program or erase them will give errors in the status register. as the failure of a page program operation does not affect the data in other pages in the same block, the block can be replaced by re-program- ming the current data and copying the rest of the replaced block to an available valid block. the copy back program command can be used to copy the data to a valid block. see the ? copy back program ? section for more de- tails. refer to table 13. for the recommended proce- dure to follow if an error occurs during an opera- tion. table 13. block failure figure 20. bad block management flowchart operation recommended procedure erase block replacement program block replacement or ecc read ecc ai07588c start end no yes yes no block address = block 0 data = ffh? last block? increment block address update bad block table
31/57 nand128-a, nand256-a, nand512-a, nand01g-a figure 21. garbage collection garbage collection when a data page needs to be modified, it is faster to write to the first available page, and the previous page is marked as invalid. after several updates it is necessary to remove invalid pages to free some memory space. to free this memory space and allow further pro- gram operations it is recommended to implement a garbage collection algorithm. in a garbage col- lection software the valid pages are copied into a free area and the block containing the invalid pag- es is erased (see figure 21. ). wear-leveling algorithm for write-intensive applications, it is recommend- ed to implement a wear-leveling algorithm to monitor and spread the number of write cycles per block. in memories that do not use a wear-leveling algo- rithm not all blocks get used at the same rate. blocks with long-lived data do not endure as many write cycles as the blocks with frequently-changed data. the wear-leveling algorithm ensures that equal use is made of all the available write cycles for each block. there are two wear-leveling levels: first level wear-leveling, new data is programmed to the free blocks that have had the fewest write cycles second level wear-leveling, long-lived data is copied to another block so that the original block can be used for more frequently- changed data. the second level wear-leveling is triggered when the difference between the maximum and the min- imum number of write cycles per block reaches a specific threshold. error correction code an error correction code (ecc) can be imple- mented in the nand flash memories to identify and correct errors in the data. for every 2048 bits in the device it is recommend- ed to implement 22 bits of ecc (16 bits for line par- ity plus 6 bits for column parity). an ecc model is available in vhdl or verilog. contact the nearest st microelectronics sales of- fice for more details. figure 22. error detection valid page invalid page free page (erased) old area ai07599b new area (after gc) new ecc generated during read xor previous ecc with new ecc all results = zero? 22 bit data = 0 yes 11 bit data = 1 no 1 bit data = 1 correctable error ecc error no error ai0833 2 >1 bit = zero? yes no
nand128-a, nand256-a, nand512-a, nand01g-a 32/57 hardware simulation models behavioral simulation models. denali software corporation models are platform independent functional models designed to assist customers in performing entire system simulations (typical vhdl/verilog). these models describe the logic behavior and timings of nand flash devices, and so allow software to be developed before hard- ware. ibis simulations models. ibis (i/o buffer infor- mation specification) models describe the behav- ior of the i/o buffers and electrical characteristics of flash devices. these models provide information such as ac characteristics, rise/fall times and package me- chanical data, all of which are measured or simu- lated at voltage and temperature ranges wider than those allowed by target specifications. ibis models are used to simulate pcb connec- tions and can be used to resolve compatibility is- sues when upgrading devices. they can be imported into spicetools.
33/57 nand128-a, nand256-a, nand512-a, nand01g-a program and erase times and endurance cycles the program and erase times and the number of program/ erase cycles per block are shown in ta- ble 14. table 14. program, erase times and program erase endurance cycles maximum rating stressing the device above the ratings listed in ta- ble 15., absolute maximum ratings , may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 15. absolute maximum ratings note: 1. minimum voltage may undershoot to ?2v for less than 20ns during transitions on input and i/o pins. maximum voltage may o ver- shoot to v dd + 2v for less than 20ns during transitions on i/o pins. parameters nand flash unit min typ max page program time 200 500 s block erase time 2 3ms program/erase cycles (per block) 100,000 cycles data retention 10 years symbol parameter value unit min max t bias temperature under bias ? 50 125 c t stg storage temperature ? 65 150 c v io (1) input or output voltage 1.8v devices ? 0.6 2.7 v 3 v devices ? 0.6 4.6 v v dd supply voltage 1.8v devices ? 0.6 2.7 v 3 v devices ? 0.6 4.6 v
nand128-a, nand256-a, nand512-a, nand01g-a 34/57 dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristics tables that follow, are de- rived from tests performed under the measure- ment conditions summarized in table 16., operating and ac measurement conditions . designers should check that the operating condi- tions in their circuit match the measurement condi- tions when relying on the quoted parameters. table 16. operating and ac measurement conditions table 17. capacitance note: t a = 25c, f = 1 mhz. c in and c i/o are not 100% tested. parameter nand flash units min max supply voltage (v dd ) 1.8v devices 1.7 1.95 v 3v devices 2.7 3.6 v ambient temperature (t a ) grade 1 0 70 c grade 6 ?40 85 c load capacitance (c l ) (1 ttl gate and c l ) 1.8v devices 30 pf 3v devices (2.7 - 3.6v) 50 pf 3v devices (3.0 - 3.6v) 100 pf input pulses voltages 1.8v devices 0 v dd v 3v devices 0.4 2.4 v input and output timing ref. voltages 1.8v devices 0.9 v 3v devices 1.5 v input rise and fall times 5 ns output circuit resistors, r ref 8.35 k ? symbol parameter test condition typ max unit c in input capacitance v in = 0v 10 pf c i/o input/output capacitance v il = 0v 10 pf
35/57 nand128-a, nand256-a, nand512-a, nand01g-a table 18. dc characteristics, 1.8v devices symbol parameter test conditions min typ max unit i dd1 operating current sequential read t rlrl minimum e =v il, i out = 0 ma - 8 15 ma i dd2 program - - 8 15 ma i dd3 erase - - 8 15 ma i dd5 stand-by current (cmos) 128mb, 256mb, 512mb devices e =v dd -0.2, wp =0/v dd - 10 50 a stand-by current (cmos) 512mb and 1gb dual die devices - 20 100 a i li input leakage current v in = 0 to v dd max - - 10 a i lo output leakage current v out = 0 to v dd max - - 10 a v ih input high voltage - v dd -0.4 - v dd +0.3 v v il input low voltage - -0.3 - 0.4 v v oh output high voltage level i oh = -100a v dd -0.1 - - v v ol output low voltage level i ol = 100a - - 0.1 v i ol (rb ) output low current (rb ) v ol = 0.2v 3 4 ma v lko v dd supply voltage (erase and program lockout) - - - 1.5 v
nand128-a, nand256-a, nand512-a, nand01g-a 36/57 table 19. dc characteristics, 3v devices symbol parameter test conditions min typ max unit i dd1 operating current sequential read t rlrl minimum e =v il, i out = 0 ma - 10 20 ma i dd2 program - - 10 20 ma i dd3 erase - - 10 20 ma i dd4 stand-by current (ttl), 128mb, 256mb, 512mb devices e =v ih , wp =0v/v dd - - 1 ma stand-by current (ttl) 512mb and 1gb dual die devices - - 2 ma i dd5 stand-by current (cmos) 128mb, 256mb, 512mb devices e =v dd -0.2, wp =0/v dd - 10 50 a stand-by current (cmos) 512mb and 1gb dual die devices - 20 100 a i li input leakage current v in = 0 to v dd max - - 10 a i lo output leakage current v out = 0 to v dd max - - 10 a v ih input high voltage - 2.0 - v dd +0.3 v v il input low voltage - ? 0.3 - 0.8 v v oh output high voltage level i oh = ? 400a 2.4 - - v v ol output low voltage level i ol = 2.1ma - - 0.4 v i ol (rb ) output low current (rb ) v ol = 0.4v 8 10 ma v lko v dd supply voltage (erase and program lockout) - - - 2.5 v
37/57 nand128-a, nand256-a, nand512-a, nand01g-a table 20. ac characteristics for command, address, data input note: 1. if t elwl is less than 10ns, t wlwh must be minimum 35ns, otherwise, t wlwh may be minimum 25ns. symbol alt. symbol parameter 1.8v devices 3v devices unit t allwl t als address latch low to write enable low al setup time min 0 0 ns t alhwl address latch high to write enable low t clhwl t cls command latch high to write enable low cl setup time min 0 0 ns t cllwl command latch low to write enable low t dvwh t ds data valid to write enable high data setup time min 20 20 ns t elwl t cs chip enable low to write enable low e setup time min 0 0 ns t whalh t alh write enable high to address latch high al hold time min 10 10 ns t whall write enable high to address latch low t whclh t clh write enable high to command latch high cl hold time min 10 10 ns t whcll write enable high to command latch low t whdx t dh write enable high to data transition data hold time min 10 10 ns t wheh t ch write enable high to chip enable high e hold time min 10 10 ns t whwl t wh write enable high to write enable low w high hold time min 20 15 ns t wlwh t wp write enable low to write enable high w pulse width min 40 25 (1) ns t wlwl t wc write enable low to write enable low write cycle time min 60 50 ns
nand128-a, nand256-a, nand512-a, nand01g-a 38/57 table 21. ac characteristics for operations note: 1. the time to ready depends on the value of the pull-up resistor tied to the ready/busy pin. see figures 34 , 35 and 36 . 2. to break the sequential read cycle, e must be held high for longer than t ehel . 3. es = electronic signature. symbol alt. symbol parameter 1.8v devices 3v devices unit t allrl1 t ar address latch low to read enable low read electronic signature min 10 10 ns t allrl2 read cycle min 10 10 ns t bhrl t rr ready/busy high to read enable low min 20 20 ns t blbh1 ready/busy low to ready/busy high read busy time, 128mb, 256mb, 512mb dual die max 12 12 s read busy time, 512mb, 1gb max 15 12 s t blbh2 t prog program busy time max 500 500 s t blbh3 t bers erase busy time max 3 3 ms t blbh4 reset busy time, during ready max 5 5 s t whbh1 t rst write enable high to ready/busy high reset busy time, during read max 5 5 s reset busy time, during program max 10 10 s reset busy time, during erase max 500 500 s t cllrl t clr command latch low to read enable low min 10 10 ns t dzrl t ir data hi-z to read enable low min 0 0 ns t ehbh t cry chip enable high to ready/busy high (e intercepted read) max 60 + t r (1) 60 + t r (1) ns t ehel t ceh chip enable high to chip enable low (2) min 100 100 ns t ehqz t chz chip enable high to output hi-z max 20 20 ns t elqv t cea chip enable low to output valid max 45 45 ns t rhbl t rb read enable high to ready/busy low max 100 100 ns t rhrl t reh read enable high to read enable low read enable high hold time min 15 15 ns t rhqz t rhz read enable high to output hi-z min 15 15 ns max 30 30 t rlrh t rp read enable low to read enable high read enable pulse width min 30 30 ns t rlrl t rc read enable low to read enable low read cycle time min 60 50 ns t rlqv t rea read enable low to output valid read enable access time max 35 35 ns read es access time (3) t whbh t r write enable high to ready/busy high read busy time, 128mb, 256mb, 512mb dual die max 12 12 s read busy time, 512mb, 1gb max 15 12 s t whbl t wb write enable high to ready/busy low max 100 100 ns t whrl t whr write enable high to read enable low min 80 60 ns t wlwl t wc write enable low to write enable low write cycle time min 60 50 ns
39/57 nand128-a, nand256-a, nand512-a, nand01g-a figure 23. command latch ac waveforms figure 24. address latch ac waveforms note: address cycle 4 is only requi red for 512mb and 1gb devices. ai08028 cl e w al i/o tclhwl telwl twhcll twheh twlwh tallwl twhalh command tdvwh twhdx (cl setup time) (cl hold time) (data setup time) (data hold time) (alsetup time) (al hold time) (e setup time) (e hold time) ai08029 cl e w al i/o twlwh telwl twlwl tcllwl twhwl talhwl tdvwh twlwl twlwl twlwh twlwh twlwh twhwl twhwl twhdx twhall tdvwh twhdx tdvwh twhdx tdvwh twhdx twhall adrress cycle 1 twhall (al setup time) (al hold time) adrress cycle 4 adrress cycle 3 adrress cycle 2 (cl setup time) (data setup time) (data hold time) (e setup time)
nand128-a, nand256-a, nand512-a, nand01g-a 40/57 figure 25. data input latch ac waveforms figure 26. sequential data output after read ac waveforms note: 1. cl = low, al = low, w = high. twhclh cl e al w i/o tallwl twlwl twlwh twheh twlwh twlwh data in 0 data in 1 data in last tdvwh twhdx tdvwh twhdx tdvwh twhdx ai08030 (data setup time) (data hold time) (alsetup time) (cl hold time) (e hold time) e ai08031 r i/o rb trlrl trlqv trhrl trlqv data out data out data out trhqz tbhrl trlqv trhqz tehqz (read cycle time) (r accesstime) (r high holdtime)
41/57 nand128-a, nand256-a, nand512-a, nand01g-a figure 27. read status register ac waveform figure 28. read electronic signature ac waveform note: refer to table 12. for the values of the manufacturer and device codes. telwl tdvwh status register output 70h cl e w r i/o tclhwl twhdx twlwh twhcll tcllrl tdzrl trlqv tehqz trhqz twhrl telqv twheh ai08032 (data setup time) (data hold time) 90h 00h man. code device code cl e w al r i/o trlqv read electronic signature command 1st cycle address manufacturer and device codes ai08039b (read es access time) tallrl1
nand128-a, nand256-a, nand512-a, nand01g-a 42/57 figure 29. page read a/ read b operation ac waveform note: address cycle 4 is only requi red for 512mb and 1gb devices. tehel cl e w al r i/o rb twlwl twhbl tallrl2 00h or 01h data n data n+1 data n+2 data last trhbl tehbh twhbh trlrl tehqz trhqz ai08033b busy command code address n input data output from address n to last byte or word in page add.n cycle 1 add.n cycle 4 add.n cycle 3 add.n cycle 2 (read cycle time) trlrh tblbh1
43/57 nand128-a, nand256-a, nand512-a, nand01g-a figure 30. read c operation, one page ac waveform note: 1. a0-a7 is the address in the spare memory area, where a0-a3 are valid and a4-a7 are ?don?t care?. cl e w al r i/o rb twhall data m data last tallrl2 ai08035 twhbh tbhrl 50h add. m cycle 1 add. m cycle 4 add. m cycle 3 add. m cycle 2 busy command code address m input data output from m to last byte or word in area c
nand128-a, nand256-a, nand512-a, nand01g-a 44/57 figure 31. page program ac waveform note: address cycle 4 is only requi red for 512mb and 1gb devices. cl e w al r i/o rb sr0 ai08037 n last 10h 70h 80h page program setup code confirm code read status register twlwl twlwl twlwl twhbl tblbh2 page program address input data input add.n cycle 1 add.n cycle 4 add.n cycle 3 add.n cycle 2 (write cycle time) (program busy time)
45/57 nand128-a, nand256-a, nand512-a, nand01g-a figure 32. block erase ac waveform note: address cycle 3 is required for 512mb and 1gb devices only. figure 33. reset ac waveform d0h 60h sr0 70h ai08038b twhbl twlwl tblbh3 block erase setup command block erase cl e w al r i/o rb confirm code read status register block address input (erase busy time) (write cycle time) add. cycle 1 add. cycle 3 add. cycle 2 w r i/o rb tblbh4 al cl ffh ai08043 (reset busy time)
nand128-a, nand256-a, nand512-a, nand01g-a 46/57 ready/busy signal electrical characteristics figures 35 , 34 and 36 show the electrical charac- teristics for the ready/busy signal. the value re- quired for the resistor r p can be calculated using the following equation: so, where i l is the sum of the input currents of all the devices tied to the ready/busy signal. r p max is determined by the maximum value of t r . figure 34. ready/busy ac waveform figure 35. ready/busy load circuit figure 36. resistor value versus waveform timings for ready/busy signal note: t = 25c. r p min v ddmax v olmax ? () i ol i l + ----------------------------------------------------------- - = r p min 1.8v () 1.85v 3ma i l + --------------------------- = r p min 3v () 3.2v 8ma i l + --------------------------- = ai07564b busy v oh ready v dd v ol t f t r ai07563b r p v dd v ss rb device open drain output ibusy ai07565b r p (k ?) 12 34 100 300 200 t r , t f (ns) 1 2 3 1.7 0.85 30 1.7 1.7 1.7 1.7 t r t f ibusy 0 400 4 r p (k ?) 12 34 100 300 200 1 2 3 ibusy (ma) 2.4 1.2 0.8 0.6 100 200 300 400 3.6 3.6 3.6 3.6 0 400 4 v dd = 1.8v, c l = 30pf v dd = 3.3v, c l = 100pf t r , t f (ns) ibusy (ma) 60 90 120 0.57 0.43
47/57 nand128-a, nand256-a, nand512-a, nand01g-a package mechanical figure 37. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package outline note: drawing is not to scale. table 22. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.100 0.050 0.150 0.0039 0.0020 0.0059 a2 1.000 0.950 1.050 0.0394 0.0374 0.0413 b 0.220 0.170 0.270 0.0087 0.0067 0.0106 c 0.100 0.210 0.0039 0.0083 cp 0.080 0.0031 d1 12.000 11.900 12.100 0.4724 0.4685 0.4764 e 20.000 19.800 20.200 0.7874 0.7795 0.7953 e1 18.400 18.300 18.500 0.7244 0.7205 0.7283 e 0.500 ? ? 0.0197 ? ? l 0.600 0.500 0.700 0.0236 0.0197 0.0276 l1 0.800 0.0315 3 0 5 3 0 5 tsop-g b e die c l a1 e1 e a a2 1 24 48 25 d1 l1 cp
nand128-a, nand256-a, nand512-a, nand01g-a 48/57 figure 38. usop48 ? lead plastic ultra thin small outline,12 x 17mm, package outline note: drawing not to scale. table 23. usop48 ? lead plastic ultra thin small outline, 12 x 17mm, package mechanical data symbol millimeters inches typ min max typ min max a 0.48 0.65 0.019 0.026 a1 0.00 0.10 0.000 0.004 a2 0.52 0.48 0.56 0.020 0.019 0.022 b 0.16 0.13 0.23 0.006 0.005 0.009 c 0.10 0.08 0.17 0.004 0.003 0.007 d1 12.00 11.90 12.10 0.472 0.469 0.476 ddd 0.06 0.002 e 17.00 16.80 17.20 0.669 0.661 0.677 e1 15.40 15.30 15.50 0.606 0.602 0.610 e0.50? ?0.020? ? l 0.55 0.45 0.65 0.022 0.018 0.026 l1 0.25 ? ? 0.010 ? ? q0505 wsop-a b e die c a1 e1 e a a2 1 24 48 25 d1 ddd l1 l
49/57 nand128-a, nand256-a, nand512-a, nand01g-a figure 39. vfbga55 8 x 10mm - 6x8 active ball array, 0.80mm pitch, package outline note: drawing is not to scale table 24. vfbga55 8 x 10mm - 6x8 ball array, 0.80mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a1.050.041 a1 0.25 0.010 a2 0.70 0.028 b 0.45 0.40 0.50 0.018 0.016 0.020 d 8.00 7.90 8.10 0.315 0.311 0.319 d1 4.00 0.157 d2 5.60 0.220 ddd 0.10 0.004 e 10.00 9.90 10.10 0.394 0.390 0.398 e1 5.60 0.220 e2 8.80 0.346 e0.80? ?0.031? ? fd 2.00 0.079 fd1 1.20 0.047 fe 2.20 0.087 fe1 0.60 0.024 sd 0.40 0.016 se 0.40 0.016 d1 d e b sd bga-z61 ddd a2 a1 a se e2 fe1 e1 e d2 fe fd1 fd
nand128-a, nand256-a, nand512-a, nand01g-a 50/57 figure 40. tfbga55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, package outline note: drawing is not to scale table 25. tfbga55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a1.200.047 a1 0.25 0.010 a2 0.80 0.031 b 0.45 0.40 0.50 0.018 0.016 0.020 d 8.00 7.90 8.10 0.315 0.311 0.319 d1 4.00 0.157 d2 5.60 0.220 ddd 0.10 0.004 e 10.00 9.90 10.10 0.394 0.390 0.398 e1 5.60 0.220 e2 8.80 0.346 e0.80? ?0.031? ? fd 2.00 0.079 fd1 1.20 0.047 fe 2.20 0.087 fe1 0.60 0.024 sd 0.40 0.016 se 0.40 0.016 d1 d e b sd bga-z61 ddd a2 a1 a se e2 fe1 e1 e d2 fe fd1 fd
51/57 nand128-a, nand256-a, nand512-a, nand01g-a figure 41. vfbga63 9x11mm - 6x8 active ball array, 0.80mm pitch, package outline note: drawing is not to scale. table 26. vfbga63 9x11mm - 6x8 active ball array, 0.80mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.05 0.041 a1 0.25 0.010 a2 0.70 0.028 b 0.45 0.40 0.50 0.018 0.016 0.020 d 9.00 8.90 9.10 0.354 0.350 0.358 d1 4.00 0.157 d2 7.20 0.283 ddd 0.10 0.004 e 11.00 10.90 11.10 0.433 0.429 0.437 e1 5.60 0.220 e2 8.80 0.346 e0.80??0.031? ? fd 2.50 0.098 fd1 0.90 0.035 fe 2.70 0.106 fe1 1.10 0.043 sd 0.40 ? ? 0.016 ? ? se 0.40 ? ? 0.016 ? ? e d e d1 sd fd se b a2 fe a1 a bga-z75 ddd fd1 d2 e2 e1 e fe1 ball "a1"
nand128-a, nand256-a, nand512-a, nand01g-a 52/57 figure 42. tfbga63 9x11mm - 6x8 active ball array, 0.80mm pitch, package outline note: drawing is not to scale table 27. tfbga63 9x11mm - 6x8 active ball array, 0.80mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.20 0.047 a1 0.25 0.010 a2 0.80 0.031 b 0.45 0.40 0.50 0.018 0.016 0.020 d 9.00 8.90 9.10 0.354 0.350 0.358 d1 4.00 0.157 d2 7.20 0.283 ddd 0.10 0.004 e 11.00 10.90 11.10 0.433 0.429 0.437 e1 5.60 0.220 e2 8.80 0.346 e0.80? ?0.031? ? fd 2.50 0.098 fd1 0.90 0.035 fe 2.70 0.106 fe1 1.10 0.043 sd 0.40 ? ? 0.016 ? ? se 0.40 ? ? 0.016 ? ? e d eb sd se a2 a1 a bga-z53 ddd fd1 d2 e2 e fe ball "a1" fe1 e e1 d1 fd
53/57 nand128-a, nand256-a, nand512-a, nand01g-a part numbering table 28. ordering information scheme devices are shipped from the factory with the memory content bits, in valid blocks, erased to ?1?. for further information on any aspect of this device, please contact your nearest st sales office. example: nand512r3a 0 a za 1 t device type nand = nand flash memory density 128 = 128mb 256 = 256mb 512 = 512mb 01g = 1gb operating voltage r = v dd = 1.7 to 1.95v w = v dd = 2.7 to 3.6v bus width 3 = x8 4 = x16 family identifier a = 528 bytes/ 264 word page device options 0 = no options 2 = chip enable don?t care enabled product version a = first version b = second version c = third version package n = tsop48 12 x 20mm (all devices) v = usop48 12 x 17 x 0.65mm (128mbit, 256mbit and 512mbit devices) za = vfbga55 8 x 10 x 1mm, 6x8 ball array, 0.8mm pitch (128mbit and 256mbit devices) zb = tfbga55 8 x 10 x 1.2mm, 6x8 ball array, 0.8mm pitch (512mbit dual die devices) za = vfbga63 9 x 11 x 1mm, 6x8 ball array, 0.8mm pitch (512mbit devices) zb = tfbga63 9 x 11 x 1.2mm, 6x8 ball array, 0.8mm pitch (1gbit dual die devices) temperature range 1 = 0 to 70 c 6 = ?40 to 85 c option blank = standard packing t = tape & reel packing e = lead free package, standard packing f = lead free package, tape & reel packing
nand128-a, nand256-a, nand512-a, nand01g-a 54/57 appendix a. hardware interface examples nand flash devices can be connected to a micro- controller system bus for code and data storage. for microcontrollers that have an embedded nand controller the nand flash can be connect- ed without the addition of glue logic (see figure 43. ). however a minimum of glue logic is required for general purpose microcontrollers that do not have an embedded nand controller. the glue logic usually consists of a flip-flop to hold the chip enable, address latch enable and com- mand latch enable signals stable during com- mand and address latch operations, and some logic gates to simplify the firmware or make the de- sign more robust. figure 44. gives an example of how to connect a nand flash to a general purpose microcontroller. the additional or gates allow the microcontrol- ler?s output enable and write enable signals to be used for other peripherals. the or gate between a3 and csn maps the flip-flop and nand i/o in different address spaces inside the same chip se- lect unit, which improves the setup and hold times and simplifies the firmware. the structure uses the microcontroller dma (direct memory access) en- gines to optimize the transfer between the nand flash and the system ram. for any interface with glue logic, the extra delay caused by the gates and flip-flop must be taken into account. this delay must be added to the mi- crocontroller?s ac characteristics and register set- tings to get the nand flash setup and hold times. for mass storage applications (hard disk emula- tions or systems where a huge amount of storage is required) nand flash memories can be con- nected together to build storage modules (see fig- ure 45. ). figure 43. connection to microcontroller, without glue logic ai08045b r w i/o e al cl w g csn ad(24:16) microcontroller nand flash dq wp rb pwaiten ad17 ad16 v dd v dd or v ss or general purpose i/o
55/57 nand128-a, nand256-a, nand512-a, nand01g-a figure 44. connection to microcontroller, with glue logic figure 45. building storage modules related documentation stmicroelectronics has published a set of application notes to support the nand flash memories. they are available from the st website www.st.com . or from your local st distributor. ai07589 r w i/o e al cl clk d2 d1 d0 q0 q1 q2 w g csn a3 a0 a1 a2 microcontroller nand flash dq d flip-flop ai08331 w nand flash device 1 g e 1 cl al nand flash device 3 nand flash device 2 nand flash device n+1 nand flash device n e 2 e 3 e n e n+1 i/o0-i/o7 or i/o0-i/o15 rb
nand128-a, nand256-a, nand512-a, nand01g-a 56/57 revision history table 29. document revision history date version revision details 06-jun-2003 1.0 first issue 07-aug-2003 2.0 design phase 27-oct-2003 3.0 engineering phase 03-dec-2003 4.0 document promoted from target specification to preliminary data status. v cc changed to v dd and i cc to i dd . title of table 2. . changed to ? product description ? and page program typical timing for nandxxxr3a devices corrected. table 1., product list , inserted on page 2. 13-apr-2004 5.0 wsop48 and vfbga55 packages added, vfbga63 (9 x 11 x 1mm) removed. figure 19., cache program operation , modified and note 2 modified. note removed for t wlwh timing in table 20., ac characteristics for command, address, data input . meaning of t blbh4 modified, partly replaced by t whbh1 and t whrl min for 3v devices modified in table 21., ac characteristics for operations . references removed from related documentation section and reference made to st website instead. figure 6. , figure 7. , figure 29. and figure 32. modified. read electronic signature paragraph clarified and figure 28., read electronic signature ac waveform , modified. note 2 to figure 30., read c operation, one page ac waveform , removed. note 3 to table 7., address insertion, x16 devices removed. only 00h pointer operations are valid before a cache program operation. i dd4 removed from table 18., dc characteristics, 1.8v devices . note added to figure 32., block erase ac waveform . small text changes. 28-may-2004 6.0 tfbga55 package added (mechanical data to be announced). 512mb dual die devices added. figure 19., cache program operation modified. package code changed for tfbga63 8.5 x 15 x 1.2mm, 6x8 ball array, 0.8mm pitch (1gbit dual die devices) in table 28., ordering information scheme . 02-jul-2004 7.0 cache program removed from document. tfbga55 package specifications added ( figure 40., tfbga55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, package outline and table 25., tfbga55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, package mechanical data ). test conditions modified for v ol and v oh parameters in table 19., dc characteristics, 3v devices . 01-oct-2004 8.0 third part number corrected in table 1., product list . 512 mbit dual die information added to table 10., copy back program addresses . block erase last address cycle modified. definition of a bad block modified in bad block management paragraph. rohs compliance added to summary description . figure 3., logic block diagram modified. document promoted from preliminary data to full datasheet status. 03-dec-2004 9.0 automatic page 0 read at power-up option no longer available. pc demo board with simulation software removed from list of available development tools. chip enable (e) paragraph clarified. 13-dec-2004 10.0 r ref parameter added to table 16., operating and ac measurement conditions . description of the family clarified in the summary description section. 25-feb-2005 11.0 wsop48 replaced with usop48 package, vfbga63 (8.5 x 15 x 1mm) replaced with vfbga63 (9 x 11 x 1mm) package, tfbga63 (8.5 x 15 x 1mm) replaced with tfbga63 (9 x 11 x 1.2mm) package. changes to table 21. , table 18. and table 2.
57/57 nand128-a, nand256-a, nand512-a, nand01g-a information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as cr itical components in life support dev ices or systems without express wr itten approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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